Thermal management of 3D IC integration with TSV (through silicon via)

Abstract

Thermal performances of 3D stacked TSV (through silicon via) chips filled with copper are investigated based on heat-transfer CFD (computational fluid dynamic) analyses. Emphases are placed on the determination of (1) empirical equations for the equivalent thermal conductive of chips with various copper-filled TSV diameters, pitches, and aspect ratios, (2) the junction temperature and thermal resistance of 3D stacking of up to 8 TSV chips, and (3) the effect of thickness of the TSV chip on its hot spot temperature. Useful design charts and guidelines are provided for engineering practice convenient.