Resonance and damping in CMOS circuits with on-chip decoupling capacitance

Abstract

Design of on-chip decoupling capacitance and modeling of resonance effects in the power supply network of CMOS integrated circuits is addressed. The modeling is based on mathematical limits proving that damping will be low, resulting in resonance unless careful design is used. Design strategies that reduce resonance are discussed. It is shown that an optimal parasitic resistor in series with the decoupling capacitor gives a maximum damping factor of 0.5 and practical values are within the range 0.3-0.4. Examples of digital circuits show that proper design of on-chip decoupling capacitance may reduce the number of bonding wires by an order of magnitude. The modeling and design suggestions are also applicable to mixed-mode circuits. In particular, sampled analog networks benefit with a potentially higher sampling rate if enhanced damping is introduced during design.