New Journal of Physics · 2014 · 55 citations · 20 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureComputer NetworksParallel ComputingClock Distribution NetworksClock ManagementClock SynchronizationDelay ModelingTime SynchronizationTiming AnalysisClock Synchronization Under Network DelayClocking ArchitectureDelay-locked LoopsPhase LockingPhase-locked LoopsPhase-locked OscillatorsSignal TransmissionSynchronization With Delays
Electronic components that perform tasks in a concerted way rely on a common time reference. For instance, parallel computing demands synchronous clocking of multiple cores or processors to reliably carry out joint computations. Here, we show that mutually coupled phase-locked loops (PLLs) enable synchronous clocking in large-scale systems with transmission delays. We present a phase description of coupled PLLs that includes filter kernels and delayed signal transmission. We find that transmission delays in the coupling enable the existence of stable synchronized states, while instantaneously coupled PLLs do not tend to synchronize. We show how filtering and transmission delays govern the collective frequency and the time scale of synchronization.
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Networks on chips: a new SoC paradigm
Luca Benini, Giovanni De Micheli · Computer · 2002 · 3.7K citations · Full text
The Kuramoto model: A simple paradigm for synchronization phenomena
Juan A. Acebrón, L. L. Bonilla, C. J. Pérez Vicente et al. · Reviews of Modern Physics · 2005 · 3.5K citations · Full text
Natural Sciences, Biology, Physics +16