Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research

TLDR

Odin II builds on the original Odin open‑source synthesis tool, adding a unified environment for front‑end parsing and netlist flattening. The authors present Odin II as a Verilog HDL synthesis framework that lets researchers explore novel HDL elaboration techniques and demonstrate its use in three ASIC and FPGA experiments. Odin II provides a unified synthesis environment that parses Verilog, flattens netlists, interfaces directly with VPR for FPGA mapping, and can ingest downstream CAD netlists for analysis. The tool’s output integrates with standard FPGA and ASIC back‑end flows, enabling quantification of synthesis improvements, and it is released as open source under the MIT License.

Abstract

In this work, we present Odin II, a framework for Verilog Hardware Description Language (HDL) synthesis that allows researchers to investigate approaches/improvements to different phases of HDL elaboration that have not been previously possible. Odin II's output can be fed into traditional back-end flows for both FPGAs and ASICs so that these improvements can be better quantified. Whereas the original Odin [1] provided an open source synthesis tool, Odin II's synthesis framework offers significant improvements such as a unified environment for both front-end parsing and netlist flattening. Odin II also interfaces directly with VPR [2], a common academic FPGA CAD flow, allowing an architectural description of a target FPGA as an input to enable identification and mapping of design features to custom features. Furthermore, Odin II can also read the netlists from downstream CAD stages into its netlist data-structure to facilitate analysis. Odin II can be used for a wide range of experiments; in this paper, we show three specific instances of how Odin II can be used by ASIC and FPGA researchers for more than basic synthesis. Odin II is open source and released under the MIT License.