2002 · 12 citations · 3 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysReconfigurable ComputingAccelerator ArchitectureDigital Signal ProcessingField-programmable Gate Array ArchitectureFine-grained Reconfigurable ArchitecturesFpga ArchitectureHardware AccelerationAdaptive Signal ProcessingMultiplier DesignMultipliersReconfigurable ArchitecturesReconfigurable Signal ProcessingReconfigurable Signal Processing ArchitecturesReconfigurationThroughput
This paper looks at various XC6200 multiplier architectures for use within adaptive signal processing systems. It compares data throughput, block utilisation and reconfiguration times. A number of approaches are compared including fully programmable multipliers and three separate ways of implementing reconfigurable multipliers. The paper shows how fixed coefficient multipliers can be used to increase the number of multipliers from 4 to 10. Many of the ideas and rules can be extended to more recent fine grain architectures.
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