IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1993 · 177 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringAlgorithmsComputer ArchitectureParallel ComputingDigital Signal ProcessingParallel ArchitecturesMulti-digit MultiplicationMultiplier DesignMultipliersPartitioning
The architecture of a design method for an M-bit by N-bit Booth encoded parallel multiplier generator are discussed. An algorithm for reducing the delay inside the branches of the Wallace tree section is explained. The final step of adding two N+or-M-1-bit numbers is done by an optimal carry select adder stage. The algorithm for optimal partitioning of the N+or-M-1-bit adder is also presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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High-Speed Arithmetic in Binary Computers
O. L. Macsorley · Proceedings of the IRE · 1961 · 622 citations
O. J. Bedrij · IRE Transactions on Electronic Computers · 1962 · 391 citations