Multiple-gate SOI MOSFETs: device design guidelines

TLDR

The study simulates various SOI MOSFET architectures, including double, triple‑gate, and gate‑all‑around devices, and introduces the Pi‑gate concept. Simulations varied gate length, channel width, doping concentration, and silicon film thickness to map the optimal design space for four gate structures. The Pi‑gate device, which is easier to fabricate, delivers electrical performance comparable to gate‑all‑around MOSFETs and shows promise for future nanometer applications, with efficiency depending on the studied parameters.

Abstract

This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.