Latchup in merged triple well structure

Abstract

In advanced CMOS, RF CMOS, and RF BiCMOS, structures which allow the separation of the p-well from the low doped p- substrate to form an "isolated MOSFET" are advantageous; this technology is also referred to as "triple well" technology. As practiced today, circuit designers desire to re-map dual-well structures to triple well implementations without a change in the on-chip design, ground-rules, or p+/n+ spacing rules. As a result, "triple well" is being practiced not as isolated regions but "merged triple well" where the n-well and associated isolating buried layers are integrated. This paper compares latchup measurements with standard dual-well implementation to a merged triple well implementation in a high resistivity p- substrate wafer. The results are shown with standard dual-well structures, and the merged triple well structures in a BiCMOS SiGe technology. Physical models are developed to explain the enhancement and reduction effects of latchup in merged triple well technology.