Impact of lithography variability on statistical timing behavior

Abstract

We describe a numerical model for chip level lithography variability analysis. Gate level critical dimensions are adjusted based on lithographic variability simulations and these perturbed gate lengths are input to a chip timing analyzer. Statistical modeling studies highlight the interaction between lithography variability and chip timing performance including the role of lithography error correlation length, optical proximity effect residuals, exposure system imperfections and photomask errors. Understanding these relationships is a critical building block for lithographic error tolerancing, design manufacturability improvement and lithography limited yield enhancements on integrated circuits for which timing is a key performance metric.