Publication | Closed Access
Porous silicon technology for RF integrated circuit applications
24
Citations
5
References
2002
Year
Unknown Venue
Electrical EngineeringPorous Silicon TechnologyEngineeringRf SemiconductorAdvanced Packaging (Semiconductors)MicrofabricationNanoelectronicsWafer Scale ProcessingCoplanar Transmission LinesApplied PhysicsSemiconductor Device FabricationIntegrated CircuitsPorous Silicon LayersElectronic PackagingSilicon On InsulatorMicroelectronicsCircuit Process
Coplanar transmission lines were fabricated on porous silicon layers of varying thickness, in the range of 1-15 /spl mu/m, on silicon substrates. For suitably thick porous silicon regions, the capacitive coupling to the conducting silicon substrate and the associated attenuation are suppressed. The use of porous silicon layers thus provides an approach to incorporate high performance transmission lines in a silicon-based monolithic integrated circuit process.
| Year | Citations | |
|---|---|---|
Page 1
Page 1