Power dissipation analysis and optimization of deep submicron CMOS digital circuits

TLDR

The paper proposes an analytical model and design methodology to estimate and minimize standby and switching power dissipation while optimizing the power‑delay product in deep submicron CMOS digital circuits. The model employs the Berkeley Short‑Channel IGFET framework, incorporates static and dynamic power analysis across threshold voltages, and accounts for supply voltage, threshold voltage, and drain‑induced barrier lowering effects, showing good agreement with HSPICE simulations. The model accurately matches HSPICE simulation results, validating its effectiveness for power estimation.

Abstract

This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley Short-Channel IGFET model and fits HSPICE simulation results well. Static and dynamic power analysis for various threshold voltages is addressed. A design methodology to minimize the power-delay product by selecting the lower and upper bounds of the supply and threshold voltages is presented. The effects of the supply voltage, the threshold voltage, and /spl eta/, which reflects the drain induced barrier lowering, are also addressed.