Concurrent testing of VLSI circuits using conservative logic

Abstract

A concurrent error detection and design for testability technique based on conservative logic is presented. The theoretical derivations and experimental results show that conservative logic provides inherent support for concurrent error detection, and the resulting circuits can be tested using only two test patterns, independent of the function performed by the circuit. The background definitions are presented, and the fundamental conservative logic theory is developed. Several example designs of adder and multiplier circuits are presented and analyzed to illustrate the developed theory. A possible implementation of a conservative logic gate is presented, and its use in a VLSI circuit is described. The resulting circuit has been fabricated using the MOSIS process. The primary disadvantage of the approach is shown to be the implementation technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>