PMOS Hole Mobility Enhancement Through SiGe Conductive Channel and Highly Compressive ILD- $\hbox{SiN}_{x}$ Stressing Layer

Abstract

In this letter, the SiGe-channel PMOS transistors integrated with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> stressing layer have been successfully fabricated. The performance improvements of devices with a gate length ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L_g </i> )of down to 40 nm were studied. For long-channel SiGe-channel PMOS, the mobility is at least 50% higher than that of the conventional bulk-Si PMOS. Moreover, compared to the conventional short-channel SiGe-channel devices, the highly compressive CESL stressor shows 32% current gain for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L_g </i> = 40 nm PMOS with the thinnest 9 A Si-cap. Therefore, integrating the stressed CESL technique into the SiGe-channel structure is an efficient method for improving PMOS device performance.