Application of Chemical Mechanical Polishing to the Fabrication of VLSI Circuit Interconnections

Abstract

Application of the chemical mechanical polishing of silicon dioxide used as the interlevel dielectric in the manufacture of VLSI chips has led to the development of a relatively simple process for fabrication of the device wiring on such chips. The polishing process is used to remove the interlevel dielectric from the tops of interconnect studs and produce a planarized surface ready for the next level of wiring. The characteristics of this polishing process were studied on both blanket films of oxide and on wafers with device topography. Empirical relationships were found, and the results applied to device manufacture, resulting in process simplification while increasing chip reliability and yield.