Drift-Tolerant Multilevel Phase-Change Memory

Abstract

Multilevel-cell (MLC) storage is a typical way for achieving increased capacity and thus lower cost-per-bit in memory technologies. In phase-change memory (PCM), however, MLC storage is seriously hampered by the phenomenon of resistance drift. Reference cells may be used to offer some relief, however their effectiveness is limited due to the stochastic nature of drift. In this paper, an alternative way to cope with drift in PCM is introduced, based on modulation coding. The new drift tolerant coding technique encodes information in the relative order of resistance levels in a codeword. Experimental results from a 90-nm PCM prototype chip demonstrate the effectiveness of the proposed method in offering high resilience to drift. Most notably, 4 levels/cell storage with raw bit-error-rates in the order of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> is achieved in a 200 kcell array and maintained for over 30 days after programming at room temperature.