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An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)
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Citations
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References
1996
Year
Low-power ElectronicsElectrical EngineeringEngineeringQd-ff ConfigurationApplied PhysicsComputer EngineeringA DividerDigital Circuit DesignMicroelectronicsPower ConsumptionOptoelectronicsElectronic Circuit
The developed GaAs static flip-flop operates at a data rate of 10 Gb/s with a power consumption of 2.8 mW at a supply voltage of 0.6 V. The power consumption at 10 Gb/s is 1/3 that of the lowest reported value for D-FFs. A divider using the QD-FF configuration operates at a clock frequency of 16 GHz with a power consumption of 2.4 mW at a supply voltage of 0.6 V. The power-delay product is about one-third that of the lowest reported value for dividers.
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