Design and stacking of an extremely thin chip-scale package

Abstract

This paper presents a study on package design and package stacking for the extremely thin Chip Scale Package (etCSP) that has a cavity at the center of the laminate package substrate and lead free solder halls. A 0.5mm thick CSP technology was developed and presented at the ECTC 2002. Package reliability level was proven to be robust by the cavity substrate structure. It passed MRT IEDEC Level 1, 1000 cycles of TIC (-55C/125C), 1000 hrs of T/H (85C/85%RH), IOOOhrs of HTS (150C), and 96hrs of HAST (130C/85%RH). However, because the package was face down format and the solder balls were located along the encapsulation area, the VO count was less than 200 with 12 mm body size. In order to develop a stackable, high VO count base package with a moderate VO count package mounted on top, we studied a face up design for the devices having more than 250 VOs. It was found that a 12 or 13 mm CSP could have around 300 VOs by adopting a face op format, and the total mount height was 1.2 mm after the 2 packages were stacked. In this presentation, the stackable package design and its reliability level are discussed.