Bonding interfaces in wafer-level metal/adhesive bonded 3D integration

Abstract

This paper examines the bonding interfaces in a back-end- of-line (BEOL) compatible wafer-level three-dimensional (3D) integrated circuit (IC) technology platform with wafer bonding of damascene patterned metal/adhesive surfaces. Copper and partially cured benzocyclobutene (BCB) are selected as the metal and adhesive, respectively. To prevent bonding voids and defects, the Cu-Ta-BCB, Cu-Cu, and BCB-BCB interfaces are investigated. Bonding voids and defects at the Cu-Ta-BCB and Cu-Cu interfaces are attributed to surface defects, topography, and thermomechanical stress resulting in plastic deformation of the copper during bonding. Defects observed at the BCB-BCB interface are attributed to an inability to accommodate large post-CMP topography. Short-loop wafer bonding experiments are performed using a process that eliminates the Cu/Ta interconnect structure, but provides the capability to produce controlled topography. Key parameters to prevent void formation at the BCB-BCB interface are the topography depth and pitch, as well as the BCB cure, denoted here as the crosslinking percentage. For BCB-BCB bonds formed with a partial-cure preparation of ~70-90% crosslinking, features ~1 mum in pitch are accommodated when the depth of the BCB topography is less than 12 nm. The accommodation depth is increased by a factor of ~4 with 50% crosslinked BCB.