Publication | Closed Access
Timing analysis with crosstalk as fixpoints on complete lattice
30
Citations
11
References
2001
Year
Unknown Venue
EngineeringVlsi DesignCircuit DesignClock SynchronizationTiming AnalysisHigh-performance ArchitectureComplete LatticeFormal MethodsComputer EngineeringComputer ArchitectureComputational ComplexityDelay VariationParallel ProgrammingComputer ScienceParallel ComputingTimed SystemCrosstalk EffectChaotic Iteration
Increasing delay variation due to crosstalk has a dramatic impact on deep sub-micron technologies. It is now necessary to include crosstalk in timing analysis. But timing analysis with crosstalk is a chicken-and-egg problem since crosstalk effect in turn depends on timing behavior of a circuit. In this paper, we establish a theoretical foundation for timing analysis with crosstalk. We show that solutions to the problem are fixpoints on a complete lattice. Base on that, we prove in general the convergence of any iterative approach. We also show that, starting from different initial solutions, an iterative approach will reach different fixpoints. The current prevailing practice, which starts from the worst case solution, will always reach the greatest fixpoint (which is the loosest solution). In order to reach the least fixpoint, we need to start from the best case solution. Base on chaotic iteration and heterogeneous structures of coupled circuits, we also design techniques to speed up iterations.
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