Dimple-array interconnect technique for packaging power semiconductor devices and modules

Abstract

This paper reports a simple non-wire bond interconnect technique, termed Dimple-Array Interconnect (DAI) technique for packaging power devices. Solder bumps and dimpled metal sheets that are capable of carrying large currents are utilized for interconnecting power chips. Preliminary experimental and analytical results demonstrated potential advantages of this technique such as reduced dc resistance and parasitic noises, improved heat dissipation and thermo-mechanical reliability, and lowered processing complexity. This technique also offers a potential approach for packaging power electronics modules.