Enhanced Write Performance of a 64-Mb Phase-Change Random Access Memory

H. Oh, B. Cho, W.Y. Cho, Sung Min Kang, Byung Joon Choi, Hyeongmo Kim, Kuisoon Kim, Dongjae Kim, Chanyeong Kwak, Hye Ryung Byun,

IEEE Journal of Solid-State Circuits · 2005 · 79 citations · 4 references

Concepts

Abstract

The write performance of the 1.8-V 64-Mb phase-change random access memory (PRAM) has been improved, which was developed based on 0.12-/spl mu/m CMOS technology. For the improvement of RESET and SET distributions, a cell current regulator scheme and multiple step-down pulse generator were employed, respectively. The read access time and SET write time are 68 ns and 180 ns, respectively.

References

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