Novel Dual Bit Tri-Gate Charge Trapping Memory Devices

Abstract

Dual bit operation of fabricated tri-gate nonvolatile memory devices with aggressively scaled oxide-nitride-oxide (ONO) dielectrics is presented for the first time. Compared to a planar cell, the proposed tri-gate device architecture offers higher readout currents and improved electrostatic gate control of the channel region yielding very good scalability of the devices. We have investigated devices with gate lengths in the range L/sub G/=100-220 nm and we focus on their write-erase, retention, and cycling characteristics.