Protecting circuits from the transient voltage suppressor's residual pulse during IEC 61000-4-2 stress

Abstract

The concept of the “residual pulse” from external IEC 61000-4-2 stress clamps is introduced. Values for this “residual pulse” are determined for some typical transient voltage suppressors. A method of using these data along with an IC's internal ESD protection to provide complete protection from system level stresses is proposed.