IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2003 · 43 citations · 21 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesBuilt-in Self-testClock Distribution NetworksClock ManagementCmos Circuit DesignLow-power Digital Circuit DesignPower ManagementAdiabatic LogicAnalog Built-in Self-testExperimental CharacterizationLogic Built-in Self-testLow-power MultipliersMicroprocessor Built-in Self-testMultiplier DesignPower Characterization
In this paper, we present the design and experimental evaluation of an 8-bit energy-recovery multiplier with built-in self-test logic and an internal single-phase sinusoidal power-clock generator. Both the multiplier and the built-in self-test have been designed in SCAL-D, a true single-phase adiabatic logic family. Fabricated in a 0.5-/spl mu/m standard n-well CMOS process, the chip has an active area of 0.47 mm/sup 2/. Correct chip operation has been verified for clock rates up to 140 MHz. Moreover, chip dissipation measurements correlate well with HSPICE simulation results. For a selection of biasing conditions that yield correct operation at 140 MHz, total measured average dissipation for the multiplier and the power-clock generator is 250 pJ per operation.
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Built-in logic block observation techniques
B. Koenemann · Medical Entomology and Zoology · 1979 · 445 citations
2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits
Andreas Krämer, J. S. Denker, B. Flower et al. · 1995 · 207 citations · Full text