Logic SER Reduction through Flipflop Redesign

Abstract

In this paper, we present a new flip flop sizing scheme that efficiently immunizes combinational logic circuits from the effects of radiation induced single event transients (SET). The proposed technique leverages the effect of temporal masking by selectively increasing the length of the latching windows associated with the flip flops thereby preventing faulty transients from being registered. We propose an effective flip flop sizing scheme and construct a variety of flip flop variants that function as low-pass filters for SETs and reduce the soft error rates (SER) of combinational circuits. In contrast to previously proposed flip flop designs that rely on logic duplication and complicated circuit design styles, our method provides a simple yet highly effective mechanism for logic SER reduction while incurring very small overheads in both delay (about 5 FO4) and power (about 5%). Experimental results at the circuit level on a wide range of benchmarks show 1000times reductions in SER for small increases in circuit delay and power