Short-channel performance and mobility analysis of <110>- and <100>-oriented tri-gate nanowire MOSFETs with raised source/drain extensions

Abstract

We successfully reduced the parasitic resistance of nanowire transistors (NW Tr.) by raised S/D extensions with thin spacers (<;10nm). I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> variations are suppressed by spacer thinning and parasitic capacitance increase is minimal. By adopting <;100> NW instead of <;110> NW, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> = 1mA/μm for I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> = 100nA/μm is achieved without stress techniques. Long-L mobility (μ) was systematically studied by separating top and side channel μ. μ of <;100> nFETs and <;110> pFETs (potentially-high μ) largely degrade due to side-surface roughness. Gate stress and interface traps affect μ of <;110> nFETs and <;110> pFETs, respectively.