IEEE Journal of Solid-State Circuits · 1990 · 38 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDifferential AmplifiersDigital Integrated CircuitsMixed-signal Integrated Circuit DesignMixed-signal IntegrationA-d ConversionAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital Converter DesignAnalog-to-digital ConvertersBandwidthCompensation TechniquesPower Consumption
The design of a fully differential two-step analog-to-digital converter (ADC) is presented. A sample-and-hold (S/H) circuit based on a unity-gain feedback amplifier, flash ADCs driven by differential resistor ladders, and a differential digital-to-analog converter (DAC) combined with the subtractor are described. The chip has been fabricated in a standard high-speed bipolar process and, by extensively utilizing compensation techniques, achieves +or-1 LSB integral nonlinearity and low harmonic distortion. A 75 Msample/s conversion rate not yet exceeded even by full-flash 10-b ADCs, has been achieved with a power consumption of 2 W. Due to the S/H circuit, the input bandwidth of 250 MHz; the effective resolution of 9 b at 5 MHz exhibits a gradual decrease over input frequency but still remains above 8 b up to 50 MHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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A fully parallel 10-bit A/D converter with video speed
T. Takemoto, Masasi Inoue, H. Sadamatsu et al. · IEEE Journal of Solid-State Circuits · 1982 · 39 citations
A 10 b 30 MHz two-step parallel BiCMOS ADC with internal S/H
Akira Matsuzawa, M. Kagawa, Masaaki Kanoh et al. · 1990 · 36 citations
Engineering, Computer Engineering, Electrical Engineering +17