A 10 b 30 MHz two-step parallel BiCMOS ADC with internal S/H

Abstract

A videorate 10-b analog-to-digital converter (ADC), which is suitable for application in digital video cameras or high-definition TV (HDTV) and which has 6-b coarse and 5-b fine comparators is discussed. Four circuit techniques have been developed to realize 10-b resolution: (1) an overlapped interpolation method, (2) a differential folding circuit with a current switch and a current-mode analog bus with a cascade circuit, (3) a unity-gain differential buffer for interpolation, and (4) a BiCMOS sample-and-hold (S/H) circuit using a diode bridge and a high-speed MOS-input op amp. A 30-MHz, 10-b ADC with under 0.5 least-significant-bit (LSB) differential nonlinearity (DNL) is fabricated with 1.2- mu m, 7.5-GHz BiCMOS process technology. The standard deviation in dispersion is 0.15 LSB. The ADC eliminates (1) many operational amplifiers for matching the reference voltage range of the two stages, (2) accurate transistor pair matching, and (3) droop-rate degradation caused by the input current of the bipolar transistor in the S/H circuit.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>