Nonlinear source and drain resistance in recessed-gate heterostructure field-effect transistors

Abstract

We have profiled the parasitic source and drain resistances versus current in recessed-gate HFET's with heavily-doped caps, using an InAlAs/n/sup +/-InP HFET as a vehicle. We observe a dramatic reduction in the parasitic resistances at moderate-to-high currents as significant current passes through the cap. Consequently, we note very little dependence in g, on the length of the extrinsic gate-source region. This is an experimental verification of predictions of two-layer models in the literature.