European Solid-State Circuits Conference · 2002 · 20 citations · 7 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureParallel ComputingSystem-on-chip DesignData ParallelismInstruction Set ArchitectureMemory HierarchyMemory Hierarchy DesignMemory Subsystem DesignParallel ArchitecturesData-intensive ComputingDatapath GenerationMemory BandwidthPipelined MemoryRegister File DesignRegister File OrganizationSparse Matrix AlgorithmsSparse Matrix Computation
The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system to target several classes of bandwidth-limited applications, including multimedia, pointer-based, and sparse-matrix applications. The DIVA project is building a prototype workstation-class system using PIM chips in place of standard DRAMs to demonstrate these concepts. A key component of this architecture is the Wide Word Processor, which is a 5-stage pipelined 256-bit datapath, complete with register file and ALU blocks. This component offers fine-grained data parallelism resulting in significant speedups. This paper details the design and implementation of this Wide Word Processor in TSMC 0.18µm technology.
7
Thorsten von Eicken, David Culler, Seth Copen Goldstein et al. · 1992 · 1.4K citations
Memory bandwidth limitations of future microprocessors
Doug Burger, James Goodman, Alain Kägi · 1996 · 394 citations · Full text
Subword parallelism with MAX-2
R.B. Lee · IEEE Micro · 1996 · 323 citations
The architecture of the DIVA processing-in-memory chip
Jeff Draper, Jacqueline Chame, Mary Hall et al. · 2002 · 207 citations
Mapping irregular applications to DIVA, a PIM-based data-intensive architecture
Mary Hall, Peter M. Kogge, J.G. Koller et al. · 1999 · 193 citations · Full text