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An assessment of the state-of-the-art 0.5 μm bulk CMOS technology for RF applications
71
Citations
5
References
2002
Year
Unknown Venue
EngineeringVlsi DesignDouble-polysilicon BjtsSilicon On InsulatorSemiconductor DeviceState-of-the-art 0.5NanoelectronicsMixed-signal Integrated CircuitCmos TechnologyMetal-reinforced SoiAppropriate Layout GeometryElectrical EngineeringComputer EngineeringSemiconductor Device FabricationMicroelectronicsLow-power ElectronicsRf ApplicationsApplied PhysicsRf Subsystem
We demonstrate that, given the appropriate layout geometry, state-of-the-art, salicided n-MOSFETs with 0.5 /spl mu/M drawn gates exhibit similar g/sub m/ (160 mS/mm), f/sub T/ (20 GHz), f/sub MAX/ (37 GHz), and F/sub MIN/ (1.9 dB @ 3.4 GHz) as the more costly, metal-reinforced SOI or SOS devices of identical gate length. The record f/sub MAX/ value for 0.5 /spl mu/m bulk CMOS is comparable to that of self-aligned, double-polysilicon BJTs.
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