Analysis of the impact of process variations on clock skew

TLDR

With smaller feature sizes, dense buffering schemes are used for efficient, noise‑immune clock distribution, but local MOSFET parameter variance increases with scaling, causing large intradie variability of clock buffer timing. In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits designed in deep submicrometer technologies. We applied advanced statistical simulation techniques and accurate mismatch measurement data to thoroughly characterize the impact of intradie variations on industrial clock distribution networks. We found that process variations are a significant source of clock skew, as confirmed by Monte Carlo simulations that show local device variations play a crucial role in the design and sizing of the clock distribution network.

Abstract

In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits designed in deep submicrometer technologies. With smaller feature size, the utilization of a dense buffering scheme has been proposed in order to realize efficient and noise-immune clock distribution networks. However, the local variance of MOSFET electrical parameters, such as V/sub T/ and I/sub DSS/, increases with scaling of device dimensions, thus causing large intradie variability of the timing properties of clock buffers. As a consequence, we expect process variations to be a significant source of clock skew in deep submicrometer technologies. In order to accurately verify this hypothesis, we applied advanced statistical simulation techniques and accurate mismatch measurement data in order to thoroughly characterize the impact of intradie variations on industrial clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the effect of mismatch confirmed that local device variations play a crucial role in the design and sizing of the clock distribution network.