Impact of Plasma-Assisted Atomic-Layer-Deposited Gate Dielectric on Graphene Transistors

Abstract

We report for the first time on graphene transistors that incorporate a remote plasma-assisted atomic-layer-deposited Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric that is directly deposited to chemical-vapor-deposited monolayer graphene at 100°C. Following dielectric formation, atomic force microscopy and Raman measurements show apparently uniform conformal coverage and retention of a nearly intact film with a slightly increased level of disorder and some signs of additional doping. Using this process, 3-μm gate length transistors with sub-10-nm gate insulator thickness are constructed, and electrical measurements demonstrate a drive current of 0.6 A/mm and a peak transconductance in excess of 90 mS/mm with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> = 0 V and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> = 1 V, which is greatly improved over coprocessed devices with SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interfacial layer with the same bias. With optimization, the plasma-assisted ALD of high-k dielectrics to graphene may potentially be useful for the design of future graphene-based technology.