IEEE Journal of Solid-State Circuits · 1999 · 17 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyCurrent-voltage CharacteristicsI/o ArchitectureIntegrated Circuit DesignLow-power Digital Circuit DesignBandwidthCharacteristic ImpedanceHigh-speed I/o Circuit DesignI/o Buffer DesignImpedance Matching TechniquesLow-voltage Cmos DesignOutput Resistance EnhancementPower Consumption
A current-mode bidirectional I/O buffer was designed, and the maximum effective bandwidth of 1.0 Gb/s per wire was obtained from measurements. To enhance the operating speed, the voltage swing on the transmission line was reduced to 0.5 V and the internal nodes of the buffer were designed to be low impedance nodes using the current-mode scheme. An automatic impedance-matching scheme was used to generate bias voltages, which adjust output resistance of the buffer to be equal to the characteristic impedance of the transmission line in spite of process variations. The chip was fabricated by using a 0.8-/spl mu/m CMOS technology. The chip size was 500/spl times/330 /spl mu/m/sup 2/, and the power consumption was 50 mW at a supply voltage of 3 V.
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