IEEE Journal of Solid-State Circuits · 2002 · 32 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsSemiconductor DevicesCmos Circuit DesignIntegrated Circuit DesignMemory Subsystem DesignMicroarchitecture DesignProcessor Core DesignProcessor MicroarchitectureAccelerator MicroarchitectureHigh-speed Cmos DesignHigh-speed Interface DesignLow-power MicroarchitectureMemory Bandwidth
This third-generation 1.1-GHz 64-bit UltraSPARC microprocessor provides 1-MB on-chip level-2 cache, 4-Gb/s off chip memory bandwidth, and a new 200 MHz JBus interface that supports one to four processors. The 87.5-million transistor chip is implemented in a seven-layer-metal copper 0.13-/spl mu/m CMOS process and dissipates 53 W at 1.3 V and 1.1 GHz.
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A third-generation SPARC V9 64-b microprocessor
R. Heald, K. Aingaran, C. Amir et al. · IEEE Journal of Solid-State Circuits · 2000 · 65 citations
Engineering, Computer Engineering, Electrical Engineering +17
Two FIFO ring performance experiments
Charles E. Molnar, Ian W. Jones, W.S. Coates et al. · Proceedings of the IEEE · 1999 · 53 citations
Engineering, Computer Engineering, Electrical Engineering +13
Implementation of a 3rd-generation SPARC V9 64 b microprocessor
R. Heald, K. Aingaran, C. Amir et al. · 2002 · 37 citations
UltraSPARC-III: a 3rd generation 64 b SPARC microprocessor
G. Lauterbach, D. Greenley, Sameer Ahmed et al. · 2002 · 12 citations