Two FIFO ring performance experiments

TLDR

Asynchronous circuits are often perceived to operate slower than equivalent clocked circuits. The authors demonstrate that asynchronous circuits can be as fast as clocked circuits using fabricated chips. They compare two high‑speed FIFO designs—one using the Asynchronous Symmetric Persistent Pulse Protocol with conventional latches, the other employing transition‑signaling latches that are larger but faster. Experiments in 0.6 µm CMOS and SPICE simulations show the first FIFO matches clocked shift‑register throughput (1.1 G items/s), while the second exceeds it (1.7 G items/s) and operates reliably across wide conditions.

Abstract

Asynchronous circuits are often perceived to operate slower than equivalent clocked circuits. We demonstrate with fabricated chips that asynchronous circuits can be every bit as fast as clocked circuits. We describe two high-speed first-in-first-out (FIFO) circuits that we used to compare the performance of asynchronous FIFOs with that of conventionally clocked shift registers. The first FIFO circuit uses a pulse-like protocol, which we call the Asynchronous Symmetric Persistent Pulse Protocol (asP*), to advance data along a pipeline of conventional latches. Use of this protocol requires careful management of circuit delays. The second FIFO circuit uses a transition signaling protocol and special transition latches to store data. These transition latches are fast, but they are about 50% larger than conventional latches. Measurements obtained from chips fabricated in 0.6 /spl mu/m CMOS and from SPICE simulations show that the throughput of the first FIFO design matches that of a conventionally clocked shift register design, with a maximum throughput of 1.1 Giga data items per second. The throughput of the second design exceeds the performance of the asP* design and achieves a maximum throughput of 1.7 Giga data items per second. We have extensively tested the chips and have found them to operate reliably over a very wide range of conditions.