Mixed-signal System-on-a-Chip (SoC) verification based on SystemVerilog model

Abstract

Simulation speed and a lack of test approaches are the main difficulties in the mixed-signal verification of a complex System-on-a-Chip (SoC). In this paper, an equivalent high-level Radio Frequency (RF) model is created by the SystemVerilog language and integrated into a mixed-signal SoC. Such a model can be executed on a digital simulator, which is dramatically faster than the traditional method using an analog solver. Some mixed-signal verification approaches based on digital methods (including constrained random data generation, assertion-based verification, coverage-driven verification, and Verification Methodology Manual) are also presented as well as a case on the integrated SoC.