Automated Integration and Communication Synthesis of Reconfigurable MPSoC Platform

Abstract

The communication synthesis is the main problematic in the multiprocessor system-on-chip (MPSoC). To resolve this problem, several methodologies can be used. These methodologies require automated methods to specify, generate and optimize the hardware, software, and the architectural interfaces between them. In this paper, we present a methodology flow for hardware-software communication synthesis for multiprocessor system-on-chip platform which are dedicated to streaming applications. Our methodology consists of high level architecture communication synthesis from functional description of the MPSoC design. The solution that we propose consists in synthesizing a custom bus architecture for the reconfigurable computing applications, which therefore allows minimizing hardware cost in the FPGA.