The floating point performance of a superscalar SPARC processor

Abstract

The floating point performance of superscalar SPARC processors is evaluated based on empirical data horn 12 benchmarks. This evaluation is done in the context of two software instruction scheduling optimization, loop unrolling and software pipelining, and for three machine models we term, 1-scalar, 2-scalar and 4-scalar. We also consider the effect of the memory system on the performance improvements.