Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture

Abstract

With growing integration, power consumption is becoming a challenging issue for mobile systems. Todaypsilas complex SoCs integrate advanced power management strategies, at both HW and SW level. HW mechanisms such as clock gating, power switches or voltage and frequency scaling optimize dynamically the power profile. In such architectures, power estimation at application level is a major concern for proper power optimization. SystemC at the transaction level is adapted and largely adopted by the industry as a simulation tool. We propose in this paper a generic way to instrument a SystemC/TLM platform in order to model power consumption at a coarse grain. The proposed approach has been applied to model an advanced DVFS architecture based on a network-on-chip.