Array processors with pipelined optical busses

Abstract

A synchronous multiprocessor architecture based on pipelined optical bus interconnections is presented. The processors are placed in a square grid and are interconnected to one another through horizontal and vertical optical buses. This architecture has an effective diameter as small as two owing to its orthogonal bus connections, and it allows all processors to have simultaneous access to the buses owing to its capability for pipelining messages. Although the resulting architecture is meshlike and uses bus connections, it has a substantially higher bandwidth than conventional and bus-augmented mesh computers. Moreover, it has a simple control structure and is universal in that various well-known multiprocessor interconnections can be efficiently embedded in it. This architecture appears to be a good candidate for hybrid optical-electronic systems in the next generation of parallel computers.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>