Module assignment and interconnect sharing in register-transfer synthesis of pipelined data paths

Abstract

The authors present a novel approach to the problem of register-transfer (RT) design optimization of pipelined data paths. They perform module assignment with the goal of maximizing the interconnect sharing between RT-level components. The interconnect sharing task is modeled as a constrained clique partitioning problem. They have developed a fast and efficient polynomial time heuristic procedure to solve this problem. This procedure is 30-50 times faster than other existing heuristics while still producing better results for the authors' purposes.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>