An efficient electrical addressing method using through-wafer vias for two-dimensional ultrasonic arrays

Abstract

This paper presents a technology for high density and low parasitic capacitance electrical interconnects to arrays of Capacitive Micromachined Ultrasonic Transducers (CMUTs) on a silicon chip. Vertical wafer feedthroughs (vias) connect an array of sensors or actuators from the front side (transducer side) to the backside (packaging side) of the chip. A 20 to 1 high aspect ratio 20 /spl mu/m diameter via is achieved by using Deep Reactive Ion Etching (DRIE). Reduction of the parasitic capacitance of the polysilicon pads to the substrate can be achieved by using Metal Insulator Semiconductor (MIS) operating in the depletion region. This three-dimensional architecture allows for elegant packaging through simple flip-chip bonding of the chip's back side to a printed circuit board (PCB) or a signal processing chip.