IEEE Transactions on Circuits and Systems I Regular Papers · 2009 · 24 citations · 22 references
EngineeringComputer ScienceElectrical EngineeringAnalog ElectronicsDigital ImagingParallel ComputingDigital Image ProcessingDigital Signal ProcessingImage FilteringImage ProcessingImage SensorsAnalog FilteringComplexityImage Processing UnitsParallel ProcessingPixel ArchitectureResolutions
A pixel-parallel <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">self-similitude</i> computation architecture has been developed for multiple-resolution directional edge filtering based on focal-plane image processing. The <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">self-similitude</i> organization has enabled pixel-by-pixel multiple-resolution image filtering with minimal complexity in interconnects. As a result, it has become possible to accomplish any (1/2) <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -resolution directional edge filtering in ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +2) steps. An analog edge-filtering chip implemented using a switched floating-gate MOS (neuMOS) technology that is capable of performing four-directional edge filtering at full, half, and quarter resolutions was designed and fabricated in a 0.35-mum 3-metal CMOS technology. The concept has been experimentally verified using the fabricated chip, and the four-directional edge filtering at full, half, and quarter resolutions was demonstrated by measurement.
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Training support vector machines: an application to face detection
E. Osuna, Robert M. Freund · 2002 · 2.5K citations