Concepedia

A 90nm CMOS 1.2V 10b power and speed programmable pipelined ADC with 0.5pJ/conversion-step

Govert Geelen, Edward Paulus, Daniel Simanjuntak, H. Pastoor, Rene Verlinden

2006 · 42 citations · 2 references

Abstract

A 10b pipelined ADC with programmable speed and power achieves a power efficiency of 0.5pJ/conversion-step for sampling frequencies between 25 and 100MHz. Measurements show an ENOB of 9.3b, ERBW exceeding 100MHz, and THD<-65dB with a supply voltage of 1.2V. Chip area is 0.3mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 90nm digital CMOS process

References

2

A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture

Daisuke Miyazaki, Shoji Kawahito, Mamoru Furuta · IEEE Journal of Solid-State Circuits · 2003 · 58 citations

Engineering, Electrical Engineering, Analog Electronics +16

An 80 MHz 10 b pipeline ADC with dynamic range doubling and dynamic reference selection

Olaf Stroeble, V.F. Dias, C. Schwoerer · 2004 · 38 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 90nm CMOS 1.2V 10b power and speed programmable pipelined ADC with 0.5pJ/conversion-step

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Abstract

References