A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture

Abstract

A 10-b 30-MS/s low-power CMOS pipelined analog-to-digital converter (ADC) is described. The ADC using a pseudodifferential architecture and a capacitor cross-coupled sample-and-hold stage consumes 16 mW with a single 2-V supply. The chip is fabricated in a standard 0.3-μm two-poly three-metal CMOS technology. The achieved low-power dissipation normalized by the sampling frequency of 0.52 mW/MHz is superior to other high-speed low-power ADCs reported. The ADC has a signal-to-noise-and-distortion ratio of 54 dB at an input frequency of 15 MHz. The maximum differential and integral nonlinearity are 0.4 and 0.5 LSB, respectively.