2010 · 22 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringElectronic MaterialsMicroelectronicsSemiconductor DevicesDigital Integrated Circuit DesignIntegrated Circuit DesignMemory DevicesPhysical DesignVery-large-scale Integration LayoutFlash MemoryFlash Memory DevicesJunction Leakage CurrentMemory Cell DesignMemory Circuit DesignNand Flash MemoryNon-volatile Memory DesignUnit Cell Optimization
A highly manufacturable multi-level NAND flash memory with a 27nm design rule has been successfully developed for the first time. Its unit cell size is 0.00375um <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (with overhead). Self Aligned Reverse Patterning is used to improve initial Vth distribution induced from DPT (Double Patterning Technology) process. By using advanced channel doping technique, the channel junction leakage is minimized and the Vpass window is improved. The optimized doping structure and cell operation scheme are evaluated. And finally 2 and 3bit per cell operation are successfully demonstrated with flash cells of 32Gb density with reasonable reliability.
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Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lenghts
J. A. Kittl, A. Veloso, A. Lauwers et al. · 2005 · 28 citations