Strain Effects of Si and SiGe Channel on (100) and (110) Si Surfaces for Advanced CMOS Applications

Abstract

High performance SiGe channel CMOS on (100) and (110) Si surfaces with process-induced strained-Si technologies was fabricated and compared to Si channel devices. The mechanism of stress-induced performance enhancements in SiGe channel devices on both (100) and (110) surfaces was systematically investigated. Device-level piezoresistance coefficients for Si and SiGe channels were extracted from CMOS transistors with external mechanical stress applied. The results were consistent with device drive current enhancement induced by the CESL strained scheme.