2006 · 19 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringField-programmable Gate ArraysMicroelectronicsReconfigurable ComputingDigital Integrated Circuit DesignDigital Signal ProcessingField-programmable Gate Array ArchitectureFpga ArchitectureMixed-signal Integrated Circuit DesignTiming AnalysisAccuracyDelay AccuracyDynamic RangeFrequency AccuracyTime Conversion
This paper presents a design of large dynamic range accurate digitally programmable delay line with 250-ps resolution on a single field programmable gate array (FPGA) chip. This design adopts time-to-digital conversion (TDC) technology, counter-based delay technology and small range digitally programmable delay line technology. When working with an oscillator with frequency accuracy of plusmn1 ppm, and when the delay range is within 0~0.1 ms, the delay accuracy of our design can reach plusmn350 ps
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