GaAs MESFETs fabricated on Si substrates using a SrTiO₃ buffer layer

Abstract

Heteroepitaxial growth of GaAs on an Si substrate has been achieved through the use of crystalline SrTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> (STO) and amorphous SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> buffer layers. The buffer layers serve to accommodate some of the lattice mismatch between the substrate and the GaAs epilayers. Field-effect transistors fabricated in the GaAs epilayers show performance comparable to similar devices fabricated on GaAs substrates. The mobility in the GaAs/STO/Si sample is 2524 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs compared to a GaAs/GaAs sample with mobility of 2682 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs. A 0.7 μm gate length device has I/sub d max/ of 367 mA/mm and G/sub m max/ of 223 mS/mm. These devices also have good RF performance with f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 14.5 GHz and class AB power density of 90 mW/mm with an associated power-added efficiency of 38% at 1.9 GHz. This RF performance is within experimental error of similar devices fabricated on GaAs substrates. Preliminary reliability results show that after 800 h at 200/spl deg/C, the GaAs/STO/Si sample showed 1.2% degradation in drain current.